• DocumentCode
    2368018
  • Title

    25nm 64Gb MLC NAND technology and scaling challenges invited paper

  • Author

    Prall, Kirk ; Parat, Krishna

  • Author_Institution
    Micron Technol., Boise, ID, USA
  • fYear
    2010
  • fDate
    6-8 Dec. 2010
  • Abstract
    A highly manufacturable 25nm 64Gb NAND technology has been developed. Many physical and electrical scaling challenges were overcome. Severe scaling challenges have to be overcome to continue NAND scaling.
  • Keywords
    NAND circuits; logic design; MLC NAND technology; electrical scaling; logic design; memory size 64 GByte; size 25 nm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0163-1918
  • Print_ISBN
    978-1-4424-7418-5
  • Electronic_ISBN
    0163-1918
  • Type

    conf

  • DOI
    10.1109/IEDM.2010.5703300
  • Filename
    5703300
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2368018