BDD based synthesis of symmetric functions with full path-delay fault testability

Author

Shi, Junhao ; Fey, Görschwin ; Drechsler, Rolf

Author_Institution

Inst. of Comput. Sci., Bremen Univ., Germany

fYear

2003

fDate

16-19 Nov. 2003

Firstpage

290

Lastpage

293

Abstract

A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. BDDs are used for the synthesis step. Only one additional input and one inverter are needed to achieve 100% Path Delay Fault (PDF) testability. The size of the circuit is guaranteed to be at most quadratic in the number of inputs. The test vectors for any PDF can be generated in linear time. Experimental results underline the efficiency of the technique. In contrast to previous approaches, the technique can also be applied to multi-output functions.

Keywords

Boolean functions; VLSI; binary decision diagrams; design for testability; fault simulation; logic CAD; logic testing; BDD based synthesis; CUDD; fault model; multi-output functions; number of inputs; robust path delay fault testability; totally symmetric Boolean functions; Binary decision diagrams; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Design automation; Design for testability; Inverters; Logic arrays; Logic circuit testing; Logic testing; Propagation delay; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2003. ATS 2003. 12th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1951-2

Type

conf

DOI

10.1109/ATS.2003.1250825

Filename

1250825