Test synthesis for datapaths using datapath-controller functions

Author

Inoue, Michiko ; Suzuki, Kazuhiro ; Okamoto, Hiroyuki ; Fujiwara, Hideo

Author_Institution

Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan

fYear

2003

fDate

16-19 Nov. 2003

Firstpage

294

Lastpage

299

Abstract

This paper proposes a test syntheses method for datapaths. The proposed method goes on design-for-testability while generating control sequences for justification and propagation at register-transfer level. Since the method fully utilizes functions of controllers as well as datapaths, it achieves small area overhead.

Keywords

automatic test pattern generation; design for testability; logic CAD; logic testing; tree searching; at-speed testing; branch-and-bound algorithm; control sequences; datapath-controller functions; datapaths test synthesis; design-for-testability; hierarchical test generation; integration approach; register-transfer level; small area overhead; Circuit faults; Circuit testing; Controllability; Costs; Design automation; Design for testability; Design methodology; Hardware; High level synthesis; Information science; Logic circuit testing; Pattern analysis; Tree searching;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2003. ATS 2003. 12th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1951-2

Type

conf

DOI

10.1109/ATS.2003.1250826

Filename

1250826

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2368096