DocumentCode
2368167
Title
Test time minimization for hybrid BIST of core-based systems
Author
Jervan, Gert ; Eles, Petru ; Peng, Zebo ; Ubar, Raimund ; Jenihhin, Maksim
Author_Institution
Embedded Syst. Lab., Linkoping Univ., Sweden
fYear
2003
fDate
16-19 Nov. 2003
Firstpage
318
Lastpage
323
Abstract
This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper, we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.
Keywords
built-in self test; integrated circuit testing; iterative methods; logic testing; system-on-chip; ATE; SoC test time minimization; core test set; hybrid BIST; iterative algorithm; memory constraints; multiple core-based systems; off-line generated deterministic test patterns; online generated pseudorandom test patterns; Assembly systems; Built-in self-test; Costs; Embedded computing; Embedded system; Hybrid power systems; Integrated circuit testing; Iterative methods; Laboratories; Logic circuit testing; Self-testing; System testing; System-on-a-chip; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2003. ATS 2003. 12th Asian
ISSN
1081-7735
Print_ISBN
0-7695-1951-2
Type
conf
DOI
10.1109/ATS.2003.1250830
Filename
1250830
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