• DocumentCode
    2368175
  • Title

    Optimization of mixed logic circuits with application to a 64-bit static adder

  • Author

    Wan, Yuanzhong ; Shams, Maitham

  • Author_Institution
    Carleton Univ., Ottawa, Ont., Canada
  • fYear
    2005
  • fDate
    3-7 Jan. 2005
  • Firstpage
    261
  • Lastpage
    266
  • Abstract
    In this paper, a CMOS logic delay optimization algorithm was used to find the optimal number of pass transistors to use for buffer insertion into a CPL chain. The result was then used as a guide during the design of a 64-bit high-speed static adder. Simulation results indicated a worst-case critical-path delay of 650 ps for a device based on TSMC 0.18 μm technology.
  • Keywords
    CMOS logic circuits; adders; circuit optimisation; delays; logic design; 0.18 micron; 64 bits; 650 ps; CMOS logic delay optimization; CPL chain; TSMC technology; buffer insertion; mixed logic circuits; pass transistors; static adder; Adders; CMOS digital integrated circuits; Capacitance; Delay; Design optimization; Inverters; Logic circuits; MOS devices; MOSFETs; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2005. 18th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2264-5
  • Type

    conf

  • DOI
    10.1109/ICVD.2005.132
  • Filename
    1383286
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2368175