Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models

SCRs have been playing an increasingly significant role in ESD protection for CMOS technologies. A major challenge is to develop effective compact simulation models for these devices valid under ESD stress conditions. A simple macro modeling approach is presented for SPICE simulation of LVTSCR devices. The method uses advanced standard BJT and MOS models such as BSIM4 and Mextram. The simulation results have been verified using VFTLP and standard TLP measurements. The method provides a practical simulation tool for ESD protection circuits using LVTSCRs.