DocumentCode
2368226
Title
Soft error rate modeling and analysis of SOI/TFT SRAM´s
Author
Oldiges, P.
Author_Institution
Digital Equipment Corp., Hudson, MA, USA
fYear
1996
fDate
2-4 Sept. 1996
Firstpage
107
Lastpage
108
Abstract
Addresses methods to increase the maximum allowable gain including lifetime reduction, decreasing SOI film thickness and increasing the channel doping. The effect of lowered power supply voltages on the gain of the parasitic device and ramifications of that for the SER of SOI SRAMs is also discussed.
Keywords
SRAM chips; doping profiles; integrated circuit modelling; integrated circuit reliability; silicon-on-insulator; thin film transistors; SER; SOI film thickness; SOI/TFT SRAM; channel doping; lifetime reduction; maximum allowable gain; parasitic device; power supply voltages; soft error rate modeling; Bipolar transistors; Circuit simulation; Error analysis; Gain control; MOSFETs; Parasitic capacitance; Performance gain; Random access memory; Switches; Thin film transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 1996. SISPAD 96. 1996 International Conference on
Print_ISBN
0-7803-2745-4
Type
conf
DOI
10.1109/SISPAD.1996.865297
Filename
865297
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