A low-cost jitter measurement technique for BIST applications

Author

Huang, Jui-Jer ; Huang, Jiun-Lang

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2003

fDate

16-19 Nov. 2003

Firstpage

336

Lastpage

339

Abstract

In this paper, we present a technique to measure the RMS period jitter of the signal under test. In the proposed approach, the lead/lag relationships between the signal under test and two delayed versions of itself are compared. The collected information corresponds to two points along the jitter´s cumulative distribution function (CDF) curve from which the RMS period jitter value can be derived. Currently, SPICE simulation results show less than 5% error for RMS jitter values ranging from 40 to 60 ps.

Keywords

SPICE; built-in self test; circuit simulation; delays; integrated circuit testing; jitter; statistical distributions; 40 to 60 ps; BIST applications; CDF; RMS period jitter; SPICE simulation error values; delayed signals; jitter cumulative distribution function curve; lead/lag relationships; low-cost jitter measurement technique; signal under test; Built-in self-test; Circuit testing; Delay effects; Delay lines; Distribution functions; Electronic equipment testing; Integrated circuit testing; Jitter; Linearity; Measurement techniques; SPICE; Self-testing; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2003. ATS 2003. 12th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1951-2

Type

conf

DOI

10.1109/ATS.2003.1250833

Filename

1250833