A numerical model for simulating MOSFET gate current degradation by considering the interface state generation

Author

Yih, C.M. ; Chung, Steve S. ; Hsu, Charles C H

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1996

fDate

2-4 Sept. 1996

Firstpage

115

Lastpage

116

Abstract

In this paper, a new gate current degradation model for n-MOSFET´s by considering the interface state generation is proposed. This interface state has been characterized using a new approach and incorporated into a 2D device simulation for predicting the device gate current characteristics due to a hot carrier stress induced effect. Good agreement of the gate current has been achieved as compared with the measurement data for both fresh and stressed devices. This model is not only useful for predicting the gate current degradation, but also as a superior monitor to substrate current for submicron device reliability issues, in particular EPROM or flash EPROM devices.

Keywords

EPROM; MOS memory circuits; MOSFET; electric current; hot carriers; interface states; semiconductor device models; semiconductor device reliability; 2D device simulation; MOSFET gate current; NMOSFET; flash EPROM devices; gate current characteristics; gate current degradation; gate current degradation model; hot carrier stress; interface state generation; n-MOSFET; numerical model; submicron device reliability; Current measurement; Degradation; EPROM; Hot carriers; Interface states; MOSFET circuits; Numerical models; Numerical simulation; Predictive models; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 1996. SISPAD 96. 1996 International Conference on

Print_ISBN

0-7803-2745-4

Type

conf

DOI

10.1109/SISPAD.1996.865301

Filename

865301