DocumentCode
2368338
Title
Numerical simulation of drain lag in HJFETs with a p-buffer layer
Author
Nogome, Masanobu ; Kunihiro, Kazuaki ; Ohno, Yasuo
Author_Institution
Microelectron. Res. Labs., NEC Corp., Ibaraki, Japan
fYear
1996
fDate
2-4 Sept. 1996
Firstpage
119
Lastpage
120
Abstract
Summary form only given. We studied the shielding effect of a partially depleted p-type buffer layer against traps for heterojunction FETs (HJFET). We confirmed a trade-off between the shielding and the drain parasitic capacitance. We also found a new frequency dispersion, which occurs in early stages due to the hole distribution setup time in the p-layer.
Keywords
buried layers; capacitance; deep levels; electron traps; hole traps; junction gate field effect transistors; semiconductor device models; BIUNAP-CT; HJFET; Shockley-Read-Hall statistics; deep traps; drain lag; drain parasitic capacitance; frequency dispersion; heterojunction FET; hole distribution setup time; numerical simulation; p-buffer layer; partially depleted buffer layer; shielding effect; two-dimensional device simulator; Charge carrier processes; Electrodes; FETs; Gallium arsenide; Laboratories; Microelectronics; Numerical simulation; Parasitic capacitance; Substrates; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 1996. SISPAD 96. 1996 International Conference on
Print_ISBN
0-7803-2745-4
Type
conf
DOI
10.1109/SISPAD.1996.865303
Filename
865303
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