DocumentCode :
2368369
Title :
Stress test for disturb faults in non-volatile memories
Author :
Mohammad, Mohammad Gh ; Saluja, Kewal K.
Author_Institution :
Comput. Eng. Dept., Kuwait Univ., Safat, Kuwait
fYear :
2003
fDate :
16-19 Nov. 2003
Firstpage :
384
Lastpage :
387
Abstract :
Non-volatile memories are susceptible to special type of faults known as program disturb faults. Testing for such faults requires the application of stress tests which have long application time to distinguish faulty cells from non-faulty cells. In this paper we present a new sensing scheme that can be used with stress tests to allow for efficient detection of faulty cells based on the notion of margin reads. We demonstrate the efficiency of the margin-read approach for distinguishing between faulty and fault-free cells using electrical simulations.
Keywords :
integrated circuit testing; logic testing; random-access storage; NVM cell; fault-free cells; faulty cells; margin read method; nonvolatile memories; program disturb faults; stress test sensing scheme; stress testing; Application software; Electrical fault detection; Fault detection; Insulation; Integrated circuit testing; Logic circuit testing; MOSFETs; Nonvolatile memory; Power supplies; Random access memories; Stress; Testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
ISSN :
1081-7735
Print_ISBN :
0-7695-1951-2
Type :
conf
DOI :
10.1109/ATS.2003.1250842
Filename :
1250842
Link To Document :
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