Technology for Power Integrated Circuits with Multiple Vertical Power Devices

Author

Igic, Petar ; Holland, Paul ; Batcup, Steve ; Lerner, Ralf ; Menz, Andreas

Author_Institution

Sch. of Eng., Univ. of Wales Swansea

fYear

2006

fDate

4-8 June 2006

Firstpage

1

Lastpage

4

Abstract

An original work in developing technology that allows the integration of multiple vertical power devices within power ICs has been presented in this manuscript. The developed technology uses a combination of top and back trenches as well as wafer sawing to achieve complete dielectric isolation between the silicon islands. Each silicon island is capable of holding either single vertical power device or CMOS circuitry. The test structures have been manufactured, wafer diced and individual chips packaged and tested initially for mechanical and thermal stability

Keywords

isolation technology; mechanical stability; power integrated circuits; power semiconductor devices; silicon; thermal stability; CMOS circuitry; Si; dielectric isolation; mechanical stability; power integrated circuits; silicon islands; thermal stability; vertical power devices; wafer dicing; wafer sawing; CMOS technology; Circuit testing; Dielectrics; Integrated circuit technology; Isolation technology; Manufacturing; Packaging; Power integrated circuits; Sawing; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE International Symposium on

Conference_Location

Naples

Print_ISBN

0-7803-9714-2

Type

conf

DOI

10.1109/ISPSD.2006.1666113

Filename

1666113