DocumentCode :
2368553
Title :
Application of DC transfer characteristics in the elimination of redundant vectors for transient noise characterization of static CMOS circuits
Author :
Chandrasekar, Sreeram ; Visvanathan, V. ; Varshney, Gaurav Kumar
Author_Institution :
ASIC Product Dev., Texas Instrum., Bangalore, India
fYear :
2005
fDate :
3-7 Jan. 2005
Firstpage :
336
Lastpage :
341
Abstract :
Static noise analysis (SNA) has become the most adopted method for crosstalk noise analysis on multi-million gate designs. Since SNA is vectorless, there exists a need to determine the correct (worst) input vector (the combination of the states of other input pins) for every signal arc in the cell library, to perform noise immunity and noise propagation analysis. In case of tools with transistor level analysis capability, in situ identification of the worst vector is needed. In the case of gate level SNA, library data needs to be modeled appropriately. Noise data characterization amounts to more than 50% of the entire library characterization time, and hence it becomes a bottleneck to on-time library delivery and time to market. Most of the runtime is due to the large number of vectors that need to be characterized for each arc. In this paper, we present a novel method to eliminate redundant vectors and identify the worst vector for noise characterization. For each arc, we use the DC transfer characteristics to identify the worst case vector. The method has been incorporated in the cell library characterization system. From testing on 130nm, 90nm and 65nm libraries, we see that our method reduces the noise characterization effort by three times.
Keywords :
CMOS digital integrated circuits; crosstalk; integrated circuit design; integrated circuit noise; transient analysis; 130 nm; 65 nm; 90 nm; DC transfer characteristics; cell library characterization; crosstalk noise analysis; input vector; noise immunity; noise propagation; on-time library delivery; redundant vector elimination; static CMOS circuits; static noise analysis; time to market; transient noise characterization; transistor level analysis; Circuit analysis; Circuit noise; Crosstalk; Libraries; Performance analysis; Pins; Runtime; Signal analysis; Testing; Time to market;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2005. 18th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2264-5
Type :
conf
DOI :
10.1109/ICVD.2005.55
Filename :
1383298
Link To Document :
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