• DocumentCode
    2368760
  • Title

    Influence of leakage reduction techniques on delay/leakage uncertainty

  • Author

    Tsai, Yuh-Fang ; Vijaykrishnan, N. ; Xie, Yuan ; Irwin, Mary Jane

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
  • fYear
    2005
  • fDate
    3-7 Jan. 2005
  • Firstpage
    374
  • Lastpage
    379
  • Abstract
    One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques on delay/leakage uncertainty is examined through Monte-Carlo analysis. The techniques investigated in this paper include increasing gate length, stack forcing, body biasing, and Vdd/Vth optimization. The impact of technology scaling and temperature sensitivity on the uncertainty reduction are also evaluated. We investigate the uncertainty-power-delay trade-off and suggest techniques for designs targeting different requirements.
  • Keywords
    Monte Carlo methods; circuit optimisation; delays; integrated circuit design; leakage currents; low-power electronics; Monte Carlo analysis; body biasing; delay/leakage uncertainty; gate length; integrated circuit design; leakage power; leakage reduction; stack forcing; uncertainty-power-delay trade-off; Computer science; Delay; Design engineering; Energy consumption; Frequency; Leakage current; Power engineering and energy; Threshold voltage; Transistors; Uncertainty;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2005. 18th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2264-5
  • Type

    conf

  • DOI
    10.1109/ICVD.2005.111
  • Filename
    1383304