Title :
Process and design optimization of a protection scheme based on NMOSFETs with ESD implant in 65nm and 45nm CMOS technologies
Author :
Chatty, K. ; Alvarez, D. ; Gauthier, R. ; Russ, C. ; Abou-Khalil, M. ; Kwon, B.J.
Author_Institution :
IBM Syst. & Technol. Group, Essex
Abstract :
Process and design optimization of NMOSFETs with ESD implant is presented. A 2 V reduction in trigger voltage, a 30% higher failure current, 50% reduction in on-resistance is achieved with a 13X increase in leakage current for a 2.5 V NMOSFET. Self-protected NMOSFETs with ESD implant enables 40% or larger decrease in NMOSFET area for a non-mixed voltage and mixed voltage I/O.
Keywords :
CMOS integrated circuits; MOSFET; electrostatic discharge; optimisation; CMOS technologies; ESD implant; NMOSFET; failure current; optimization; trigger voltage; CMOS process; CMOS technology; Design optimization; Electrostatic discharge; Failure analysis; Implants; Leakage current; MOSFET circuits; Protection; Voltage;
Conference_Titel :
29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-58537-136-5
DOI :
10.1109/EOSESD.2007.4401777
