Title :
Testability improvement during high-level synthesis
Author :
Safari, Saeed ; Esmaeilzadeh, Hadi ; Jahangir, Amir-Hossein
Author_Institution :
CE Dept., Sharif Univ. of Technol., Tehran, Iran
Abstract :
Improving testability during the early stages of High-Level Synthesis (HLS) reduces test hardware overheads, test costs, design iterations, and also improves fault coverage. In this paper, we present a novel register allocation algorithm which is based on weighted graph coloring, targeting testability improvement.
Keywords :
design for testability; graph colouring; high level synthesis; logic testing; design iterations; extended conflict graph; fault coverage; greedy algorithm; high-level synthesis; register allocation algorithm; test costs; test hardware overheads; testability improvement; weighted graph coloring; Automatic test pattern generation; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Costs; Design for testability; Electrocardiography; Graph theory; High level synthesis; High-level synthesis; Logic circuit testing; Merging; Registers;
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
Print_ISBN :
0-7695-1951-2
DOI :
10.1109/ATS.2003.1250874
