Title :
Test pattern length required to reach the desired fault coverage
Author_Institution :
Matsushita Electr. Ind. Co., Ltd., Kyoto, Japan
Abstract :
In this study, we defined the relationship between the fault coverage and the execution test pattern and found the validity of our theory by proving that this relationship agrees with the actual values using single stuck-at fault coverage as the fault coverage. We believe that our theory will enable the prediction of the execution test pattern length (=testing time) and ATPG processing time required to reach the desired fault coverage at an early stage of the design of the devices and to provide early solutions for problems arising during test development.
Keywords :
VLSI; automatic test pattern generation; design for testability; integrated circuit testing; ATPG processing time; VLSI testing; desired fault coverage; execution test pattern; negative binominal distribution; pattern compression coefficient; single stuck-at fault coverage; test pattern length; Automatic test pattern generation; Built-in self-test; Cities and towns; Costs; Design for testability; Distribution functions; Equations; Fault detection; Integrated circuit testing; Test pattern generators; Testing; Very large scale integration; Very-large-scale integration;
Conference_Titel :
Test Symposium, 2003. ATS 2003. 12th Asian
Print_ISBN :
0-7695-1951-2
DOI :
10.1109/ATS.2003.1250878
