• DocumentCode
    2368963
  • Title

    A solution for an ideal planar multi-gates process for ultimate CMOS?

  • Author

    Monfray, S. ; Huguenin, J.L. ; Martin, M. ; Samson, M.P. ; Borowiak, C. ; Arvet, C. ; Dalemcourt, JF ; Perreau, P. ; Barnola, S. ; Bidal, G. ; Denorme, S. ; Campidelli, Y. ; Benotmane, K. ; Leverd, F. ; Gouraud, P. ; Le-Gratiet, B. ; De-Buttet, C. ; Pinze

  • fYear
    2010
  • fDate
    6-8 Dec. 2010
  • Abstract
    We demonstrate for the first time high-performant planar multi-gates devices with Si-conduction channel of 4nm, allowing drive current up to 1350μA/μm @Ioff=0.4nA/μm (Vdd=1.1V, CET=1.9nm). But as future multi-gates transistors need to have reduced capacitances and a simple robust process, we also demonstrate in this paper an ideal planar self-aligned solution, based on the direct exposure of a HSQ layer through a 5nm Si-channel. This opens the way to an easy planar multi-gate process for ultimate CMOS (11nm node & below), fully co-integrable with conventional devices.
  • Keywords
    CMOS integrated circuits; elemental semiconductors; silicon; transistors; CMOS; HSQ layer; Si; conduction channel; planar multi-gates process; size 5 nm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0163-1918
  • Print_ISBN
    978-1-4424-7418-5
  • Electronic_ISBN
    0163-1918
  • Type

    conf

  • DOI
    10.1109/IEDM.2010.5703339
  • Filename
    5703339
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2368963