DocumentCode
236900
Title
Analysis of Power Distribution Network in glass, silicon interposer and PCB
Author
Youngwoo Kim ; Kiyeong Kim ; Jonghyun Cho ; Joungho Kim ; Sundaram, Venky ; Tummala, Rao
Author_Institution
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
fYear
2014
fDate
4-8 Aug. 2014
Firstpage
470
Lastpage
474
Abstract
3D integration using a glass interposer and through glass via technologies is expected to improve the performance of a whole system significantly. However, due to the high quality factor of the glass substrate, the sharp impedance peaks on the Power Distribution Networks arise at the resonances. When the mode resonances occur, performance of a whole system could be degraded. Segmentation based impedance-estimation was used to analyze the PDN impedance and analyzed system degradation at resonance frequencies. To maximize advantages of the glass interposers, the PDN should be carefully designed to suppress the resonances. Considering the current status of the glass fabrication processes, we propose that placing the ground vias near the signal vias is the most promising solution for maximizing the advantages of the glass interposers.
Keywords
electronics packaging; elemental semiconductors; glass; integrated circuit design; printed circuits; silicon; three-dimensional integrated circuits; 3D integration; PCB; Si; glass interposer; glass substrate; high quality factor; impedance estimation; power distribution network; resonance frequencies; silicon interposer; Glass; Impedance; Insertion loss; Noise; Resonant frequency; Silicon; Substrates; PDN; glass; interposer; pcb; resonance; segmentation method; silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Electromagnetic Compatibility (EMC), 2014 IEEE International Symposium on
Conference_Location
Raleigh, NC
Print_ISBN
978-1-4799-5544-2
Type
conf
DOI
10.1109/ISEMC.2014.6899018
Filename
6899018
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