Title :
A mesochronous physical link architecture for network-on-chip interconnects
Author :
Vitullo, Francesco ; Insalata, Nicola E L ; Petri, Esa ; Casula, Michele ; Saponara, Sergio ; Fanucci, Luca ; Locatelli, Riccardo ; Coppola, Marcello
Author_Institution :
Univ. of Pisa, Pisa
Abstract :
Clock distribution is a major issue when implementing system-on-a-chip in deep sub-micron technologies. This work presents a new mesochronous physical link architecture, named SKIL, which enables full bandwidth communication between macrocells clocked by signals with the same frequency and an arbitrary amount of skew. SKIL is implemented using standard-cells design flows. It introduces two clock cycles of latency and negligible area and leakage power overheads. Implementation results are presented on a 65 nm CMOS technology.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit interconnections; network-on-chip; CMOS technology; cells design flows; clock distribution; deep submicron technologies; latency clock cycles; leakage power overheads; mesochronous physical link architecture; negligible area; network-on-chip interconnects; size 65 nm; skew insensitive link; system-on-a-chip; Bandwidth; CMOS technology; Clocks; Delay lines; Frequency synchronization; Macrocell networks; Metastasis; Network-on-a-chip; Signal generators; System-on-a-chip;
Conference_Titel :
Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4244-1000-2
Electronic_ISBN :
978-1-4244-1001-9
DOI :
10.1109/RME.2007.4401803
