On finding consecutive test vectors in a random sequence for energy-aware BIST design

During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying "useless" test vectors that do not contribute to fault dropping. For low-power testing, modification logic/ROM may be used to skip the LFSR states that generate useless test patterns. The overhead of extra logic increases rapidly with the number of such jumps. Since identification of useless patterns strongly depends on the order in which incremental fault simulation is performed, an elegant solution to this problem would be to find a minimum set of segments in the LFSR sequence, where each segment corresponds to a consecutive subsequence of useful test patterns. This is formulated as consecutive test cover (CTC) problem, where the objective is to optimize a cost function combining the number of segments and the number of useful test patterns. The proposed heuristic algorithm to solve the CTC problem includes a "gap" parameter to allow a controllable number of useless patterns. Experiments on ISCAS-89 benchmark circuits reveal considerable reduction in the number of segments without any degradation of mode led fault coverage.