Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application

Author

Suock Chung ; Rho, K.-M. ; Kim, S.-D. ; Suh, H.-J. ; Kim, D.-J. ; Kim, H.J. ; Lee, S.H. ; Park, J.-H. ; Hwang, H.-M. ; Hwang, S.-M. ; Lee, J.-Y. ; An, Y.-B. ; Yi, J.-U. ; Seo, Y.-H. ; Jung, D.-H. ; Lee, M.-S. ; Cho, S.-H. ; Kim, J.-N. ; Park, G.-J. ; Jin,

Author_Institution

R&D Div., Hynix Semicond. Inc., Icheon, South Korea

fYear

2010

fDate

6-8 Dec. 2010

Abstract

A compact STT (Spin-Transfer Torque)-RAM with a 14F² cell was integrated using modified DRAM processes at the 54 nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level. Through the direct access capability and normal chip operation in our STT-RAM test blocks, the switching behavior of bit cell arrays was also analyzed statistically. From this data and from the scaling trend of STT-RAM, we estimate that the unit cell dimension below 30 nm can be smaller than 8F².

Keywords

DRAM chips; integrated circuit testing; magnetic tunnelling; statistical analysis; MTJ; access transistors; bit cell arrays; full integrated STT-RAM; magnetic tunnel junction; modified DRAM processes; single bit cell level; size 54 nm; spin-transfer torque; statistical analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0163-1918

Print_ISBN

978-1-4424-7418-5

Electronic_ISBN

0163-1918

Type

conf

DOI

10.1109/IEDM.2010.5703351

Filename

5703351