A framework for distributed and hierarchical design-for-test

As we move into the system-on-chip era, test cost is becoming a significant portion of the total cost. Similarly, test synthesis, test pattern generation, pattern compression and pattern validation are consuming significant portion of the design cycle time. The volume of test generation and validation is high due to the size of the designs as well as the types of tests that are required to be run - scan test patterns for stuck-at and delay tests, logic and memory BIST patterns, IDDQ tests, burn-in tests, and several miscellaneous tests. Designs cannot be taped out without validated test patterns. At the same time, since design timing closure takes up a significant portion of the project time and the timing information is not available until late in the schedule, there is immense pressure on the DFT team to generate and validate patterns in a small time frame. This paper describes a framework for design-for-test which exploits both hierarchy and the inherent parallelism in the DFT jobs to run the jobs in a distributed computing environment so as to minimize the runtime impact.