Massive parallelism on a chip-VLSI aspects involving dynamic logic

In most cases performance of parallel machines is proven with special applications that enable for adequate granularity, and thus are able to show the performance. Looking at common machine types, the involved techniques do not solve the problem of fast communication among processing elements. In fact, nearly any of these types is capable of really fine grain granularity. In most real applications this is not a big problem. But in a few cases this becomes critical. The presented approach shows how to cope with fast communication among processing elements. This is done through the use of massive parallelism on a single chip, or on a set of chips. In this case optimum communication speed can be assumed and thus fast processing within a very small area becomes the design goal. This design goal is met in the special case with dynamic logic enabling for a large number of very small processing elements