A hierarchical cost tree mutation approach to optimization of analog circuits

This work presents a novel method for systematic design of a composite cost function for typical analog circuit sizing optimization problems involving multiple criteria. A non-linear normalization strategy for objective functions has been proposed and has been shown to be better than the traditional linear normalization functions. A hierarchical cost tree mutation based dynamic weight adjustment algorithm has been developed, which combines the designers´ problem specific knowledge with the dynamic solution state in the current iteration to decide the weights in the next iteration. Experiments on a typical switched capacitor analog integrator circuit in 0.18μm CMOS technology show that the proposed method works well in most cases, while conventional methods fail in the more complex scenarios.