An optimized two stages low power sinc3 filter for ΣΔ modulators

Author

Lombardi, A. ; Malcovati, P. ; Basto, A. ; Bonizzoni, E. ; Maloberti, F.

Author_Institution

Univ. of Pavia, Pavia

fYear

2007

fDate

2-5 July 2007

Firstpage

81

Lastpage

84

Abstract

This paper presents the design of a low power sinc³ filter implementing a decimation factor by 16 and suitable for a second order SigmaDelta modulators running at 256 MHz. The circuit uses the cascade of two stages and consumes only 48.1 muW, with 1.2 V voltage supply. The ultra-low power features come from both an architectural optimization and the use of suitable transistor level schemes. The circuit, simulated in a 0.18-mum CMOS technology, improves the overall power consumption by about 75.4% with respect to an already optimum conventional design.

Keywords

CMOS analogue integrated circuits; FIR filters; VHF filters; cascade networks; circuit optimisation; circuit simulation; integrated circuit design; low-power electronics; sigma-delta modulation; CMOS technology; FIR filter; architectural optimization; cascaded circuits; decimation factor; frequency 256 MHz; optimized two stages low power sinc³ filter design; power 48.1 muW; power consumption; second order SigmaDelta modulators; size 0.18 mum; transistor level schemes; ultra-low power features; voltage 1.2 V; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Design optimization; Digital signal processing; Energy consumption; Finite impulse response filter; Low voltage; Power filters; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.

Conference_Location

Bordeaux

Print_ISBN

978-1-4244-1000-2

Electronic_ISBN

978-1-4244-1001-9

Type

conf

DOI

10.1109/RME.2007.4401816

Filename

4401816