PCB via to trace return loss optimization for >25Gbps serial links

High speed serial links usually have extremely tight requirement on the quality of the signal channels, in terms of insertion loss and return loss. Along with an end-to-end channel design, the transition from plated-through-hole (PTH) via to fan-out traces on printed circuit board (PCB) creates unavoidable impedance discontinuity, which greatly impacts the channel return loss performance. It is important to understand and model this discontinuity for optimization purpose. This paper discusses several approaches of improving the channel´s properties, by optimizing the via-to-trace transition. Considering the impedance continuity at via to trace fan-out region, usually bigger anti-pad size (to reduce capacitive discontinuity) and larger return-path area (to reduce inductive discontinuity) are employed. In this paper, we inserted a short segment of fan-out-traces, named as “transition traces”, with slightly lower impedance than the system impedance; it significantly helps on improving the overall return loss performance, while being able to take care of the above-mentioned capacitive and inductive discontinuities very well. Besides, the impact of various parameters, including transition trace impedance, anti-pad sizes on different layers, is analyzed; and the optimum combination of these design parameters is suggested. Lastly, the manufactured test board is measured to verify the optimization method.