Gate leakage and its reduction in deep submicron SRAM

In this work the impact of gate leakage on SRAM is described and two approaches for reducing gate leakage currents are examined in detail. In one approach, the supply voltage is reduced while in the other the potential of the ground node is raised. In both the approaches the effective voltage across SRAM cell is reduced in inactive mode using a dynamic self-controllable switch. Simulation results based on BPTM (Berkeley Predictive Technology Model) for 45nm channel length device show that the scheme in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node potential is raised. Results obtained show that 96% reduction in the leakage currents of SRAM can be achieved.