Title :
A 1.3GSample/s 10-tap full-rate variable latency self-timed FIR filter with clocked interfaces
Author :
Tierno, J. ; Rylyakov, A. ; Rylov, S. ; Singh, M. ; Ampadu, P. ; Nowick, S. ; Immediato, M. ; Gowda, S.
Author_Institution :
IBM T J. Watson Research Center
Keywords :
Circuits; Clocks; Delay; Disk drives; Finite impulse response filter; Independent component analysis; Pipelines; Power supplies; Protocols; Throughput;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992100
