Intrinsic variability in nano-CMOS design and beyond

It is widely recognized that process variations will have profound impact on nearly all aspects of future IC design. Depending on their sources, they are often categorized into two types: intrinsic variations and process-induced variations [1][2]. Process-induced variations are caused by the imperfection in silicon fabrication, varying from foundries to foundries. On the other side, intrinsic variations, induced by atom-level charge and geometry fluctuations, are inherent to the device structure. They are limited by fundamental physics, posing one of the ultimate barriers to continual technology scaling. Examples of intrinsic variations include random dopant fluctuation (RDF), line edge roughness (LER), and oxide thickness fluctuation (OTF) [2]. Their importance is rapidly increasing as device feature size approaches the atom dimension.