Algorithmic implementation of low-power high performance FIR filtering IP cores

This paper presents two schemes for the implementation of high performance and low power FIR filtering intellectual property (IP) cores. Low power is achieved through the utilization of algorithms such as coefficient segmentation, block processing and combined segmentation and block processing algorithms. On the other hand, multiple data paths are utilized for achieving high performance. The paper presents the complete architectural implementation of these algorithms for high performance applications. The paper describes the design methodology, evaluation environment, and provides results which show up to 40% reduction in power consumption.