• DocumentCode
    2369885
  • Title

    Three dimensional dimple contact technology for lower contact resistance

  • Author

    Saito, Satoshi ; Nakamura, Kazuyo ; Matsuda, Kenzo ; Sakiyama, Keizo

  • Author_Institution
    VLSI Res. Labs. Sharp Corp., Nara, Japan
  • fYear
    1991
  • fDate
    11-12 Jun 1991
  • Firstpage
    206
  • Lastpage
    212
  • Abstract
    A three dimensional dimple contact was formed by silicon etching at the bottom of the contact hole. Contact size examined were around sub-half micron. Side wall of high temperature oxide film, which has perfect stepcoverage, were used to form the sub-half micron contacts. In these dimples, arsenic ions were implanted 60 keV with a 15 degree beam tilt in order to make uniform n+diffusion layer along the silicon surface. Process conditions, ion implantation and annealing, were controlled with computer simulations. Blanket tungsten process with Ti/TiN barriers was used for filling the deep contact holes. Low contact resistance of fine contact hole with dimple was demonstrated, compared with the contact resistance of conventional contact. This three dimensional dimple contact has been found to be the one technology for lower contact resistance
  • Keywords
    VLSI; integrated circuit technology; ohmic contacts; semiconductor-metal boundaries; Si etching; Si:As; annealing; beam tilt; contact technology; ion implantation; lower contact resistance; three dimensional dimple contact; Computer simulation; Contact resistance; Etching; Ion implantation; Silicon; Simulated annealing; Surface resistance; Temperature; Tin; Tungsten;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Multilevel Interconnection Conference, 1991, Proceedings., Eighth International IEEE
  • Conference_Location
    Santa Clara, CA
  • Print_ISBN
    0-87942-673-X
  • Type

    conf

  • DOI
    10.1109/VMIC.1991.152987
  • Filename
    152987