Title :
Post-layout PCB check and simulations for signal integrity
Author :
Jiang Li ; Yingzhi Wu
Author_Institution :
Cadence Design Syst., San Jose, CA, USA
Abstract :
Overviews of comprehensive geometry-based and electrical-based PCB layout checks are given. Layout check results are then compared with signal integrity simulations at various levels: with vs. without trace couplings; with vs. without via couplings; ideal PDN vs. non-ideal PDN; partial channel vs. full channel. A DDR3 memory design is used as an example.
Keywords :
geometry; printed circuit layout; signal processing; DDR3 memory design; electrical-based layout checks; full channel; geometry-based layout checks; ideal PDN; non-ideal PDN; partial channel; post-layout PCB check; signal integrity simulations; trace couplings; via couplings; Analytical models; Computational modeling; Couplings; Impedance; Layout; Performance evaluation; Time-domain analysis;
Conference_Titel :
Electromagnetic Compatibility (EMC), 2014 IEEE International Symposium on
Conference_Location :
Raleigh, NC
Print_ISBN :
978-1-4799-5544-2
DOI :
10.1109/ISEMC.2014.6899064
