Analog circuit design at and below VT + 2Vds,sat

Author

Layton, Kent D. ; Comer, Donald T. ; Comer, David J.

Author_Institution

Brigham Young Univ., Provo

fYear

2007

fDate

2-5 July 2007

Firstpage

213

Lastpage

216

Abstract

Design methods and architectures for high-performance analog circuitry which operates at supply voltages at and below V_T + 2 V_ds,sat are developed. A low voltage amplifier is designed using these methods. The amplifier, fabricated in an AMIS 0.5 mum CMOS process with 0.8 V p-channel threshold voltages, is shown to operate at supply voltages as low as 0.75 V with full rail-to-rail input and output operation. The amplifier shows 105 dB of open loop gain and GBW of 0.31 MHz while dissipating 11.5 muW from a 0.8 V supply. The design methods may be used with advanced CMOS processes to further reduce the required analog supply voltage.

Keywords

CMOS analogue integrated circuits; amplifiers; integrated circuit design; low-power electronics; AMIS CMOS process; analog circuit design; analog supply voltage; frequency 0.31 MHz; gain 105 dB; high-performance analog circuitry architecture; low voltage amplifier; power 11.5 muW; size 0.5 mum; voltage 0.75 V; voltage 0.8 V; voltage 2 V; Analog circuits; Analog computers; CMOS process; Design engineering; Design methodology; Impedance; Low voltage; Rail to rail inputs; Resistors; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.

Conference_Location

Bordeaux

Print_ISBN

978-1-4244-1000-2

Electronic_ISBN

978-1-4244-1001-9

Type

conf

DOI

10.1109/RME.2007.4401850

Filename

4401850