DocumentCode
2370040
Title
DFM: linking design and manufacturing
Author
Raghvendra, Srinivas ; Hurat, Philippe
Author_Institution
Synopsys, Inc., Mountain View, CA, USA
fYear
2005
fDate
3-7 Jan. 2005
Firstpage
705
Lastpage
708
Abstract
Until the move to the 130nm node, yield was an issue only for product engineers and engineers on the production line. Design engineers did not need to think explicitly about yield, or understand the manufacturing process. Beginning at the 130nm node, yield has become more problematic, and the defect mechanisms that contribute to yield loss are very different. Where random defects used to be dominant, we now have defects due to lithographic issues, and pattern (or design) dependent issues. This paper explains how these latter defect mechanisms differ from random defects and how and why the design engineer needs to become involved to mitigate the problem. On the lithography topic, this paper briefly examines techniques such as OPC (optical proximity correction) and PSM (phase shift masking), and explain their design and yield impact. We also examine issues such as dummy metal fill for CMP, redundant via insertion, as ways to mitigate pattern dependent yield issues.
Keywords
chemical mechanical polishing; integrated circuit yield; manufacturing processes; nanolithography; nanopatterning; phase shifting masks; proximity effect (lithography); CMP; DFM; defect mechanisms; dummy metal fill; lithographic defects; manufacturing process; optical proximity correction; pattern dependent yield; phase shift masking; production line; random defects; yield impact; yield loss; Design engineering; Design for manufacture; Joining processes; Lithography; Manufacturing processes; Optical design; Optical design techniques; Process design; Production; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2005. 18th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2264-5
Type
conf
DOI
10.1109/ICVD.2005.80
Filename
1383357
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