• DocumentCode
    2370080
  • Title

    An accurate probabilistic model for error detection

  • Author

    Rejimon, Thara ; Bhanja, Sanjukta

  • Author_Institution
    Electr. Eng., South Florida Univ., Tampa, FL, USA
  • fYear
    2005
  • fDate
    3-7 Jan. 2005
  • Firstpage
    717
  • Lastpage
    722
  • Abstract
    We propose a novel single event fault/error model based on logic induced fault encoded directed acyclic graph (LIFE-DAG) structured probabilistic Bayesian networks, capturing all spatial dependencies induced by the circuit logic. The detection probabilities also act as a measure of soft error susceptibility (an increased threat in nanodomain logic block) that depends on the structural correlations of the internal nodes and also on input patterns. Based on this model, we show that we are able to estimate detection probabilities of single-event faults/errors on IS-CAS´85 benchmarks with high accuracy (zero-error), linear space requirement complexity, and with an order of magnitude (≈5 times) reduction in estimation time over corresponding BDD based approaches.
  • Keywords
    belief networks; error detection; logic circuits; probabilistic logic; Bayesian networks; IS-CAS´85 benchmark; LIFE-DAG; circuit logic; detection probability; error detection; error susceptibility; estimation time reduction; logic induced fault encoded directed acyclic graph; nanodomain logic block; probabilistic model; single event fault error model; Bayesian methods; Circuit faults; Combinational circuits; Electrical fault detection; Fault detection; Latches; Logic circuits; Probabilistic logic; Random variables; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2005. 18th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-2264-5
  • Type

    conf

  • DOI
    10.1109/ICVD.2005.46
  • Filename
    1383359