DocumentCode
2370102
Title
A new noise-tolerant dynamic logic circuit design
Author
Frustaci, Fabio ; Corsonello, Pasquale ; Cocorullo, Giuseppe
Author_Institution
Univ. of Calabria, Rende
fYear
2007
fDate
2-5 July 2007
Firstpage
233
Lastpage
236
Abstract
This work proposes a new noise-tolerant dynamic circuit design. It has been extensively compared to previously published schemes. The new design can achieve a level of noise robustness that is unreachable by the previous proposals. Furthermore, it has minimal delay and energy penalties. Under the same energy-delay product, the proposed design shows a noise-robustness that is increased by up to 116%, in comparison with the existing schemes.
Keywords
CMOS logic circuits; VLSI; circuit simulation; delays; integrated circuit design; integrated circuit noise; logic design; tolerance analysis; CMOS process; VLSI chips; energy penalties; energy-delay product; noise robustness level; noise-tolerant dynamic logic circuit design; Circuit noise; Clocks; Crosstalk; Delay; Integrated circuit noise; Leakage current; Logic circuits; Noise reduction; Subthreshold current; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.
Conference_Location
Bordeaux
Print_ISBN
978-1-4244-1000-2
Electronic_ISBN
978-1-4244-1001-9
Type
conf
DOI
10.1109/RME.2007.4401855
Filename
4401855
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