DocumentCode
2370154
Title
Multiple fault testing of logic resources of SRAM-based FPGAs
Author
Goyal, Saurabh ; Choudhury, Mihir ; Rao, S.S.S.P. ; Kalyan, Kumar L.
Author_Institution
Indian Inst. of Technol., Mumbai, India
fYear
2005
fDate
3-7 Jan. 2005
Firstpage
742
Lastpage
747
Abstract
We present a simple but useful method which detects all multiple stuck-at faults in the application and configuration inputs of LUTs. A novel method for testing of stuck-at faults at control bits of flip flops has also been proposed. The aim is to integrate testing of LUTs, flip flops and multiplexers which reduces the number of configurations and hence minimize the testing time.
Keywords
SRAM chips; VLSI; fault location; fault simulation; field programmable gate arrays; flip-flops; logic circuits; multiplexing equipment; LUT; SRAM FPGA; flip flop control bits; logic resources; multiple fault testing; multiplexers; stuck-at faults; testing integration; Automatic testing; Computer science; Fault detection; Field programmable gate arrays; Logic arrays; Logic design; Logic testing; Multiplexing; Sequential analysis; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2005. 18th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2264-5
Type
conf
DOI
10.1109/ICVD.2005.122
Filename
1383363
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