DocumentCode

2370162

Title

An on-chip 3MB subarray-based 3rd level cache on an itanium microprocessor

Author

Weiss, D. ; Wuu, J.J. ; Chin, V.

Author_Institution

Hewlett-Packard Company

Volume

2

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

88

Lastpage

413

Keywords

Adaptive arrays; Clocks; Decoding; Driver circuits; Feedback circuits; Flexible printed circuits; Latches; Logic arrays; Microprocessors; Repeaters;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992132

Filename

992132