Case study of fault-tolerant architectures for 90nm CMOS crythographic cores

Author

Stanisavljevic, Milos ; Gurkaynak, Frank K. ; Schmid, Alexandre ; Leblebici, Yusuf ; Gabrani, Maria

Author_Institution

Swiss Fed. Inst. of Technol. (EPFL), Lausanne

fYear

2007

fDate

2-5 July 2007

Firstpage

253

Lastpage

256

Abstract

This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128 bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been applied. One of the fault-tolerant architectures is a novel four-layer architecture exhibiting a large immunity to permanent as well as random failures. Characteristics of the averaging/ thresholding layer are emphasized. Measurement results show advantage of four-layer architecture over triple modular redundancy in terms of reliability.

Keywords

CMOS digital integrated circuits; cryptography; elemental semiconductors; fault tolerance; integrated circuit design; integrated circuit modelling; integrated circuit reliability; network topology; silicon; AES cryptographic core; CMOS crythographic cores; Si; averaging-thresholding layer characteristics; four-layer fault-tolerant architectures; reliability terms; silicon realization; size 90 nm; CMOS technology; Circuit faults; Computer architecture; Fabrication; Fault tolerance; Fault tolerant systems; Laboratories; Manufacturing; Microelectronics; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Research in Microelectronics and Electronics Conference, 2007. PRIME 2007. Ph.D.

Conference_Location

Bordeaux

Print_ISBN

978-1-4244-1000-2

Electronic_ISBN

978-1-4244-1001-9

Type

conf

DOI

10.1109/RME.2007.4401860

Filename

4401860