DocumentCode

2370298

Title

Jitter optimization based on phase-locked loop design parameters

Author

Mansuri, M. ; Chih-Kong Ken Yang

Author_Institution

University of California

Volume

2

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

102

Lastpage

421

Keywords

Bandwidth; Clocks; Damping; Delay effects; Design optimization; Phase locked loops; Phase measurement; Phase noise; Timing jitter; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992152

Filename

992152