Title :
State-of-the-art device in high voltage power ICs with lowest on-state resistance
Author :
Su, R.Y. ; Yang, F.J. ; Tsay, J.L. ; Cheng, C.C. ; Liou, R.S. ; Tuan, H.C.
Author_Institution :
Analog/Power & Specialty Technol. Div., TSMC, Hsinchu, Taiwan
Abstract :
High performance LDMOS of 600-800V Vbdss has been developed with PB (Pbody)_Extension RESURF scheme for smart power applications. This device design demonstrates the lowest specific on-state resistance against to the latest publications (40% improvement than triple RESURF, 65% improvement than double RESURF in JI LDMOSFET) in 600-800V families and breaks 1-D silicon limit. This technology also surpasses the performance in thin SOI technology, yet it uses the bulk Si material and less manufacturing processing steps.
Keywords :
MOSFET; integrated circuit design; power integrated circuits; silicon-on-insulator; LDMOSFET; RESURF; Si; high voltage power IC; on-state resistance; reduce surface field; state-of-the-art device; thin SOI technology; voltage 600 V to 800 V;
Conference_Titel :
Electron Devices Meeting (IEDM), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4424-7418-5
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2010.5703403
