Title :
Ultra-low power TFTs with 10 nm stacked gate insulator fabricated by nitric acid oxidation of Si (NAOS) method
Author :
Matsumoto, Taketoshi ; Yamada, Mikihiro ; Tsuji, Hiroshi ; Taniguchi, Kenichi ; Kubota, Yasushi ; Imai, Shigeki ; Terakawa, Sumio ; Kobayashi, Hikaru
Author_Institution :
ISIR, Osaka Univ., Ibaraki, Japan
Abstract :
We have succeeded in fabrication of ultra-low power poly-Si based thin film transistors (TFTs) with 10 nm gate insulators and 1 V driving voltage. An ultrathin interfacial SiO2 layer formed in 68 wt% nitric acid (HNO3) aqueous solutions at 120°C decreases a gate leakage current by two orders of magnitude, resulting in a high on/off ratio of 109.
Keywords :
leakage currents; oxidation; power transistors; thin film transistors; HNO3; Si (NAOS) method; SiO2; gate leakage current; nitric acid oxidation; size 10 nm; stacked gate insulator; ultra-low power TFT; ultra-low power poly-Si based thin film transistor; voltage 1 V;
Conference_Titel :
Electron Devices Meeting (IEDM), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4424-7418-5
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2010.5703405
