• DocumentCode
    2370374
  • Title

    180nm gate length amorphous InGaZnO thin film transistor for high density image sensor applications

  • Author

    Jeon, Sanghun ; Park, Sungho ; Song, Ihun ; Hur, Ji-Hyun ; Park, Jaechul ; Kim, Sunil ; Kim, Sangwook ; Yin, Huaxiang ; Lee, Eunha ; Ahn, Seungeon ; Kim, Hojung ; Kim, Changjung ; Chung, U-in

  • Author_Institution
    Semicond. Device Lab., Yongin, South Korea
  • fYear
    2010
  • fDate
    6-8 Dec. 2010
  • Abstract
    In this article, we propose a novel hybrid complementary metal oxide semiconductor (CMOS) image sensor architecture utilizing nanometer scale amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFT) combined with a conventional Si photo diode. This approach will overcome the loss of quantum efficiency and image quality due to the downscaling of the photodiode. The 180nm gate length a-IGZO TFT exhibits remarkable short channel device performance including a low 1/f noise and a high output gain, despite fabrication temperatures as low as 200°C. The excellent device performance has been achieved by a double layer gate dielectric (Al2O3/SiO2) and a trapezoidal active region formed by a tailored etching process. A self aligned top gate structure was employed for low parasitic capacitance. 3D process simulation tools were applied to optimize a four pixel CMOS image sensor structure. The results demonstrate how our stacked hybrid device approach contributes to new device strategies in image sensor architectures. We expect that this approach is applicable to numerous devices and systems in future micro- and nano-electronics.
  • Keywords
    1/f noise; CMOS image sensors; etching; gallium compounds; indium compounds; photodiodes; thin film transistors; zinc compounds; 1/f noise; 3D process simulation tool; CMOS image sensor structure; InGaZnO; hybrid complementary metal oxide semiconductor; image quality; image sensor architecture; micro-electronics; nano-electronics; nanometer scale amorphous thin film transistor; photodiode; quantum efficiency; self aligned top gate structure; silicon photo diode; stacked hybrid device approach; tailored etching process;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0163-1918
  • Print_ISBN
    978-1-4424-7418-5
  • Electronic_ISBN
    0163-1918
  • Type

    conf

  • DOI
    10.1109/IEDM.2010.5703406
  • Filename
    5703406