DocumentCode
2370457
Title
A low overhead high speed histogram based test methodology for analog circuits and IP cores
Author
Bahukudumbi, Sudarshan ; Bharath, Krishna
Author_Institution
Dept. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM, USA
fYear
2005
fDate
3-7 Jan. 2005
Firstpage
804
Lastpage
807
Abstract
In this paper we present a methodology to test complex analog circuits. We employ the proposed histogram-correlation technique to test these circuits. The test data for the circuit under test is collected on site, during the normal functioning of the circuit. This eliminates the need for complex test generators and costly testers. We also extend our methodology to test analog IP cores by designing a core test wrapper for analog circuits. Experimental results are presented for a continuous-time state-variable filter which is one of the circuits in the mixed signal benchmark initiative. The percentage deviation of correlation values for a faulty CUT ranged from 4% to 97% with an uncertainty in the fault free correlation values of about 2.2%, ensuring detection of all injected faults. The experimental results show that our proposed technique is extremely effective and is currently the best available test solution.
Keywords
analogue circuits; circuit testing; IP cores; analog circuit testing; continuous-time state-variable filter; core test wrapper; fault free correlation values; histogram test methodology; histogram-correlation technique; Analog circuits; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Educational institutions; Filters; Histograms; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2005. 18th International Conference on
ISSN
1063-9667
Print_ISBN
0-7695-2264-5
Type
conf
DOI
10.1109/ICVD.2005.16
Filename
1383374
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