Bounds on the VLSI layout complexity of homogeneous product networks

In this paper we obtain bounds on the area and wire length required by VLSI layouts of homogeneous product networks with any number of dimensions. The lower bounds are obtained by computing lower bounds on the bisection width and the crossing number. The upper bounds are derived by using traditional frameworks like separators and bifurcators, as well as a new method based on combining collinear layouts. This last method has led to the best area and wire lengths for most of the homogeneous product networks we considered