A methodology for fast vector based power supply and substrate noise analyses

Noise injection patterns very much depend on application scenarios. In this paper we propose a CAD methodology for a fast vector based power supply and substrate noise analyses. The proposed flow takes the switching events from a gate-level simulation and computes the time domain power/ground and substrate noise waveforms. The noise signatures are then combined with the respective extracted power supply and substrate network of the chip for a comprehensive analyses. Novel reduction techniques have been explored to achieve faster run times while maintaining good accuracy. Results of the flow can also be used for several other analyses like clock tree jitter, critical paths etc. In the end we present a case study where this method has been applied.