Title :
RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications
Author :
Jan, C.-H. ; Agostinelli, M. ; Deshpande, H. ; El-Tanani, M.A. ; Hafez, W. ; Jalan, U. ; Janbay, L. ; Kang, M. ; Lakdawala, H. ; Lin, J. ; Lu, Y.-L. ; Mudanai, S. ; Park, J. ; Rahman, A. ; Rizk, J. ; Shin, W.-K. ; Soumyanath, K. ; Tashiro, H. ; Tsai, C. ;
Author_Institution :
Logic Technol. Dev. (Ltd.), Intel Corp., Hillsboro, OR, USA
Abstract :
The impact of silicon technology scaling trends and the associated technological innovations on RF CMOS device characteristics are examined. The application of novel strained silicon and high-k/metal gate technologies not only benefits digital systems, but significantly improves RF performance. The peak cut-off frequency (fT) doubles from 209 GHz in the 90 nm node to 445 GHz at the 32 nm node. 1/f flicker noise reduces by an order of magnitude from the 0.13 um node to the 32 nm node. Transistor noise figure, high voltage tolerance, and quality factors of RF passives all show similar benefits from technology scaling.
Keywords :
CMOS integrated circuits; field effect MIMIC; system-on-chip; RF CMOS device characteristics; RF CMOS technology scaling; RF SoC; silicon technology scaling trend; system-on-chip; transistor noise figure;
Conference_Titel :
Electron Devices Meeting (IEDM), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4424-7418-5
Electronic_ISBN :
0163-1918
DOI :
10.1109/IEDM.2010.5703431
