• DocumentCode
    2370905
  • Title

    A diagonal interconnect architecture and its application to RISC core design

  • Author

    Igarashi, M. ; Mitsuhashi, T. ; Le, A. ; Kazi, S. ; Yang-Trung Lin ; Fujimura, A. ; Teig, S.

  • Author_Institution
    Toshiba Corporation
  • Volume
    2
  • fYear
    2002
  • fDate
    7-7 Feb. 2002
  • Firstpage
    166
  • Lastpage
    167
  • Keywords
    Clocks; Design methodology; Integrated circuit interconnections; Process design; Reduced instruction set computing; Routing; Semiconductor device modeling; Timing; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-7803-7335-9
  • Type

    conf

  • DOI
    10.1109/ISSCC.2002.992196
  • Filename
    992196
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2370905