Author :
Chidambaram, P.R. ; Gan, C. ; Sengupta, S. ; Ge, L. ; Chen, Y. ; Yang, S. ; Liu, P. ; Wang, J. ; Yang, M. ; Teng, C. ; Du, Y. ; Patel, P. ; Kamal, P. ; Bucki, R. ; Vang, F. ; Datta, A. ; Bellur, K. ; Yoon, S. ; Chen, N. ; Thean, A. ; Han, M. ; Terzioglu,
Author_Institution :
Qualcomm Inc., San Diego, CA, USA
Abstract :
With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, a cost effective 28 nm 4G SOC technology has been crafted. This 28 nm design strategy uses two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density, 55% decrease in power and 30% gain in frequency with respect to the 45 nm counterpart. Relevant technical tradeoffs between the design/technology interactions are discussed to illustrate the codesign aspects.
